Job description:

We are looking for a Junior RTL Design Engineer to join our silicon engineering team. You will design and implement synthesizable RTL for high-performance digital blocks, collaborating with senior architects to deliver PPA-optimized SoC components.

What you'll do:

• •Design and implement synthesizable RTL for high-performance digital blocks using Verilog/SystemVerilog.
• •Collaborate with senior architects to define microarchitecture and perform feasibility studies.
• •Optimize designs for PPA (Power, Performance, and Area) while ensuring functional correctness.
• •Assist in resolving timing violations and floorplanning constraints alongside the Physical Design team.

What We're Looking For

• •2–3 years of experience in digital logic design and RTL coding.
• •Proficiency in SystemVerilog and familiarity with synthesis tools (e.g., Design Compiler, Genus).
• •Fundamental understanding of clock domain crossing (CDC) and static timing analysis (STA).
• •Experience with SoC bus protocols such as AMBA (AXI, AHB, APB).

What You'll Bring

• •A bachelor's or master's degree in Electrical/Computer Engineering.
• •A proactive approach to learning and debugging complex logic issues.
• •Enthusiasm for developing cutting-edge silicon solutions in a collaborative environment.

What We Offer

• •Opportunity to work on next-generation SoC architectures.
• •Exposure to industry-leading EDA toolchains and design methodologies.
• •Mentorship from senior silicon architects and a growth-oriented culture.