Job description:

We are seeking an Entry-level Design Verification Engineer to join our hardware team. In this role, you will assist in building UVM-based verification environments, execute test plans, and work closely with design engineers to verify complex digital IPs.

What you'll do:

• •Assist in developing UVM-based verification environments and reusable testbench components.
• •Execute test plans and run simulations to verify design specifications.
• •Analyze functional coverage results and write basic constrained-random tests.
• •Work closely with design engineers to identify and debug RTL bugs.

What We're Looking For

• •0–1 year of experience in ASIC/FPGA verification.
• •Basic knowledge of SystemVerilog and an interest in UVM (Universal Verification Methodology).
• •Understanding of hardware functional coverage and simulation basics.
• •Familiarity with scripting languages like Python or Tcl.

What You'll Bring

• •Strong analytical skills and a 'break-the-design' mindset.
• •A solid foundation in digital logic and computer architecture.
• •Eagerness to learn professional verification flows and methodology.

What We Offer

• •A structured path to becoming a professional Verification Engineer.
• •Hands-on training with advanced simulation platforms.
• •A supportive environment focused on technical growth and knowledge sharing.