Job description:

We are looking for a Junior Physical Design Engineer to join our silicon implementation team. You will assist in the RTL-to-GDSII flow, perform timing closure, and run physical verification checks to deliver optimized silicon designs.

What you'll do:

• •Assist in the RTL-to-GDSII flow, including floorplanning, placement, and routing.
• •Help execute Clock Tree Synthesis (CTS) and optimize for low-power requirements.
• •Run Static Timing Analysis (STA) and assist in closing timing across various modes.
• •Perform physical verification checks such as DRC, LVS, and Antenna.

What We're Looking For

• •2–3 years of experience in physical implementation and sign-off.
• •Familiarity with industry-standard tools (e.g., Innovus, IC Compiler II, or Calibre).
• •Basic understanding of Advanced Process Nodes and physical design constraints.
• •Knowledge of IR drop analysis and power integrity basics.

What You'll Bring

• •A detail-oriented mindset with a focus on meeting PPA targets.
• •Ability to use Tcl or Python for basic task automation.
• •A collaborative spirit to bridge the gap between RTL design and silicon implementation.

What We Offer

• •Involvement in the final stages of silicon tape-outs.
• •Opportunities to work on the latest process technologies.
• •A professional environment at the heart of the NSTP tech hub.