Job Description: Design Verification Engineer

Location: Digital IC Design Lab, PG Building - SEECS (NUST)
Application Deadline:
About the Role: We are seeking a motivated Design Verification Engineer to join our team. This role offers hands-on experience in verifying SoC and IP designs. You will work closely with our design and verification teams, focusing on design verification.
Responsibilities:
  • Define verification goals and establish project milestones for SoC and IP designs.
  • Develop and execute test plans, testbenches, and verification environments.
  • Implement verification components, including basic and layered testbenches.
  • Conduct simulations, debug designs, and analyze results to resolve issues.
  • Create and execute test cases following the verification plan.
  • Document verification progress and findings in technical reports.
  • Participate in design reviews and improve verification processes.
Qualifications:
  • Bachelor's or Master's degree in Electrical or Computer Engineering.
  • Strong understanding of digital logic design principles and computer architecture.
  • Familiarity with SoC and IP design, on-chip communication protocols, and HDLs (Verilog/SystemVerilog).
  • Good understanding of verification constructs like randomization, coverage, and assertions.
  • Proficient in SystemVerilog OOP-based verification.
  • Knowledge of UVM.
  • Strong analytical and problem-solving skills.
  • Experience with formal verification tools is a plus.
Contact Information: Please send your CVs and any queries to:
Email: abid.rafique@seecs.nust.edu.pk
Phone: 0333-5549094