K2 - C4: SoC with Digital In Memory Compute (DIMC) for Ultra Low Power Edge AI
Overview
This System-on-Chip (SoC) integrates Digital In-Memory Compute (DIMC) technology to deliver high-efficiency AI processing directly within memory arrays, drastically reducing data movement and associated energy costs. Optimized for ultra-low power edge AI applications, such as always-on sensors, wearable devices, and smart endpoints, the SoC enables real-time inference at the edge with minimal power consumption. By performing computations where the data resides, it achieves significant gains in speed and energy efficiency compared to traditional von Neumann architectures, making it ideal for battery-constrained or energy-harvesting environments. The SoC also employs cryptographic accelerators with post quantum cryptography (PQC) support for secure transfer of data from the sensor to the SoC as well as from the SoC to the edge server.
Dive into the Details
01
RISC-V Core (RV32IMAC)
This SoC integrates a high-performance 32-bit RISC-V RV32IMAC processor core, supporting Multiplication (M), Atomic operations (A), and Compressed instructions (C) to optimize speed, code density, and multitasking. Bit manipulation instructions are included to enable cryptographic acceleration. With the ZiCSR extension, the core provides fast access to Control and Status Registers (CSRs), supporting real-time functions like task scheduling, interrupt handling, and exception processing required for deterministic RTOS environments.
02
Digital In-Memory Compute (DIMC) AI Accelerator
The DIMC AI Accelerator performs neural computations directly within standard SRAM arrays, bypassing traditional memory-to-processor data transfers. This dramatically reduces energy use while accelerating matrix-vector operations crucial for AI inference. Exploiting the parallelism of SRAM, the DIMC engine is ideal for low-latency, ultra-low power edge AI tasks in wearables, smart sensors, and IoT applications where energy and space constraints are critical.
03
Software Development Kit (SDK) and IDE
A dedicated SDK enables efficient deployment of Deep Neural Networks (DNNs) on the DIMC unit by providing access to memory-mapped registers and DMA controls. The Eclipse IDE is supported for C/C++ application development and includes full debugging capabilities. Additional SDKs are available for secure application development, supporting classical AES/SHA and advanced post-quantum cryptographic (PQC) functions on the SoC.
04
Real-Time Operating System (RTOS) Support
The SoC is designed to support RTOS environments, enabling multitasking in edge AI scenarios such as sensor data acquisition, processing, and communication. This is facilitated by Control and Status Registers (CSRs), ZiCSR extensions, and the Core Local Interrupt Controller (CLINT). It currently supports both Zephyr and FreeRTOS, allowing developers to build responsive, real-time systems with reliable task scheduling and control.